Field programmable gate array based upon transistor gate oxide breakdown
US6650143B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, the capacitor having a dielectric between the first and second terminal. The cell also includes a select transistor having a gate, a source, and a drain, the gate connected to the read bitline, the source connected to the switch control node, and the drain connected to a row wordline. Finally, the cell includes a switch being controlled by the switch control node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.