Full stress open digit line memory device
US6650584B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.