Exception handling with reduced overhead in a multithreaded multiprocessing system
US6651163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.