Modular architecture for memory testing on event based test system
US6651204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Apr 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31915
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.