Providing fault coverage of interconnect in an FPGA
US6651238B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.