Trench fill process for reducing stress in shallow trench isolation
US6653200B2 · kind B2 · utility
37Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of reducing stress in a shallow trench isolation region of a MOSFET device comprising the step of forming a dielectric in the shallow trench isolation region wherein the thermal expansion coefficient of the dielectric matches the thermal expansion coefficient of silicon in the substrate thereby reducing stress in the shallow trench isolation region. Also provided is a method of forming a dielectric filled, shallow trench isolation region for a MOSFET device where the shallow trench is filled with an an aluminosilicate, an aluminum silicon oxynitride or silicon oxynitride dielectric alloys.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.