Process for reducing the critical dimensions of integrated circuit device features
US6653231B2 · kind B2 · utility
13Cited by
21References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2001 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.