Three-dimensional memory array and method of fabrication
US6653712B2 · kind B2 · utility
186Cited by
24References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.