Method and apparatus for a delay lock loop
US6653875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.