Semiconductor wafer testing system and method
US6657453B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | May 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for testing a plurality of semiconductor devices of a common wafer includes a plurality of driver circuits, each operable to produce an intermediate test signal as a function of a source test signal; a plurality of sets of isolation components, each isolation component of a given set (i) receiving the intermediate test signal from one of the driver circuits associated with the set, and (ii) producing a wafer level test signal such that each wafer level test signal is at least partially electrically isolated from one another; and a plurality of wafer contactors, each coupled to a respective one of the isolation components and operable to electrically connect to one of the semiconductor devices and to conduct a respective one of the wafer level test signals to that semiconductor device, wherein the wafer contactors are coupled to the isolation components such that adjacent semiconductor devices of the wafer receive wafer level test signals from different sets of isolation components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.