Method and apparatus for specifying address offsets and alignment in logic design
US6658547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0661
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary.Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset. The incoming address port has a base address to calculate an offset address. The outgoing address port has the offset address. The offset value is a multiple of a transaction size…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.