Staged aluminum deposition process for filling vias

US6660135B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Sang Ho Yu · Cupertino, US
• Yonghwa Chris Cha · San Jose, US
• Murali Abburi · Santa Clara, US
• Shri Singhvi · Milpitas, US
• Fufa Chen · Cupertino, US

Key dates

• Filing date: Dec 21, 2001
• Grant date: Dec 9, 2003
• Expiry date: Dec 29, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76882
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor metallization process for providing complete via fill on a substrate, free of voids, and a planar metal surface, free of grooves. In one aspect, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A conformal PVD metal layer, such as Al or Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr. The vias and/or contacts are then filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably performed in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by at least 100 mm, and a hot metal PVD chamber, also serving as a reflow chamber.