Method of assembling a stackable integrated circuit chip
US6660561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable integrated circuit chip package comprising a carrier and a flex circuit. The flex circuit itself comprises a flexible substrate having opposed top and bottom surfaces, and a conductive pattern which is disposed on the substrate. The chip package further comprises an integrated circuit chip which is electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the carrier such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package. The carrier is sized and configured to be releasably attachable to the carrier of at least one other identically configured stackable integrated circuit chip package in a manner wherein the chip packages, when attached to each other, are maintained in registry along first and second axes which are generally co-planar and extend in generally perpendicular relation to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.