High density floating gate flash memory and fabrication processes therefor
US6660588B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.