Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
US6660598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.