Stand-alone triggering structure for ESD protection of high voltage CMOS

US6660602B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Vladislav Vashchenko · Palo Alto, US
• Ann Concannon · San Jose, US
• Peter J. Hopper · San Jose, US
• Marcel ter Beek · Pleasanton, US

Key dates

• Filing date: Mar 12, 2002
• Grant date: Dec 9, 2003
• Expiry date: Mar 12, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.