Testing device for testing a memory
US6661718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.