Method and device for compressing and expanding data pattern
US6661839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There are provided methods each of which is for efficiently compressing a test pattern to be applied to an IC for testing. The number of data changes &phgr; and a data entropy H of a pattern for each pin of an IC are obtained and then the test pattern is divided and the divided patterns are distributed to a block for &phgr; that is equal to or less than a threshold value &phgr;M (&phgr;<&phgr;M), a block for &phgr;>&phgr;M and for H that is equal to or less than a threshold value HM (H<HM), and a block for H>HM (411). The block for &phgr;<&phgr;M is compressed by a run length compressing method, the block for &phgr;>&phgr;M and H<HM is compressed by the run length compressing method after application of Burrows wheeler transform, and the block for H>HM is compressed by an LZ compressing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.