Polishing method and apparatus
US6663469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jun 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A semiconductor substrate having a Cu layer formed so as to fill wiring grooves formed in the substrate surface and to cover regions of the substrate surface where no wiring groove is formed is brought into sliding contact with a polishing surface on a turntable to carry out polishing until the Cu layer is polished to a predetermined thickness. Then, the semiconductor substrate is brought into sliding contact with a polishing surface on a turntable to carry out polishing until the Cu layer on the substrate surface is removed, except for portions of the Cu layer formed to fill the wiring grooves, and a barrier metal layer is also removed. Thus, the Cu layer on the substrate surface can be removed uniformly, and the Cu wiring portions formed in the wiring grooves can be planarly and uniformly polished without giving rise to problems of over-polishing such as dishing or erosion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.