Array architecture for depletion mode ferroelectric memory devices
US6665206B2 · kind B2 · utility
7Cited by
33References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.