Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6667902B2 · kind B2 · utility
123Cited by
43References
13Claims
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Key dates
| Filing date | Dec 17, 2001 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jun 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 å thickness or less, as commonly available from presently available advanced CMOS logic processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.