Method and apparatus for discharging an array well in a flash memory device
US6667910B2 · kind B2 · utility
10Cited by
7References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device is disclosed in which an erase voltage is applied to a well containing flash memory transistors during an erase operation. The well is then discharged toward ground, first by one discharge circuit which discharges the well until the voltage on the well is lower than a snap-back characteristic of a transistor employed in another well discharge circuit. After the well voltage is below the snap-back characteristic of the transistor, the well is discharged by the other discharge circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.