Semiconductor memory device and test method thereof using row compression test mode
US6667919B1 · kind B1 · utility
5Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer circuit for supplying a first voltage level to one of at least one true bitline or at least one complement bitline during a test mode; an equalizing line for coupling a plurality of equalizer circuits along a wordline; and a comparator for comparing a second voltage on the equalizing line during the test mode to a reference voltage, wherein if the second voltage is less than the reference voltage, the wordline is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.