Hierarchical verification for equivalence checking of designs
US6668362B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Mar 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining equivalence between two integrated circuit device designs. Functional blocks and compare points within a first design are compared with functional blocks and compare points in a second design to determine compare points that are matched. The integrated circuit designs are traversed net-wise and cut points are inserted at compare points that are matched and that are not determined to be constant. As each design is traversed, the design is flattened such that flat copies of both integrated circuit designs are obtained (that include the inserted cut points). The flat copies of the integrated circuit designs are then compared to determine equivalence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.