Method for an advanced MIM capacitor
US6670237B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a capacitor in a semiconductor device. An embodiment simultaneously forms a MIM capacitor and a dual damascene interconnect using common process steps. An embodiment comprises: forming a capacitor bottom plate and a first metal line over the semiconductor structure. We form a second dielectric layer over the capacitor bottom plate, the first metal line, and a first dielectric layer. Next, we form a top plate opening in the second dielectric layer to at least partially expose the capacitor bottom plate. A capacitor dielectric layer is formed over the capacitor bottom plate and the second dielectric layer. A capacitor top plate is formed in the top plate opening. Subsequently, we form a via opening through at least the second dielectric layer, the capacitor dielectric layer over the first metal line to expose a portion of the first metal line. Next, we fill the via opening with a second metal layer to form a via plug. A third dielectric layer is formed over the via plug and the capacitor top plate. We form a first trench opening and a second trench opening through the third dielectric layer, the second passivation layer and the third passivation layer. The first …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.