Method of fabricating lateral diodes and bipolar transistors
US6670255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/617
Abstract
Disclosed is a method of fabricating a lateral semiconductor device, comprising:providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.