Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size

US6670263B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Arne Ballantine · Palo Alto, US
• Kevin K. Chan · Staten Island, US
• Jeffrey D. Gilbert · Winooski, US
• Kevin M. Houlihan · Boston, US
• Glen L. Miles · South Burlington, US
• James J. Quinlivan · South Burlington, US
• Samuel C. Ramac · Beacon, US
• Michael B. Rice · Colchester, US
• Beth Ward · South Burlington, US

Key dates

• Filing date: Mar 10, 2001
• Grant date: Dec 30, 2003
• Expiry date: Mar 10, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.