Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations

US6670661B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Haneder · Hersbruck, DE
• Harald Bachhofer · Hersbruck, DE

Key dates

• Filing date: Jan 7, 2002
• Grant date: Dec 30, 2003
• Expiry date: Jan 7, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.