Methods of operating a multiple bit line column redundancy scheme having primary and redundant local and global bit lines
US6671214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Oct 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.