Method and system for managing the result from a translator co-processor in a pipelined processor
US6671793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechani…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.