Method for alignment mark formation for a shallow trench isolation process
US6673635B1 · kind B1 · utility
30Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.