Method for manufacturing a multi-bit memory cell

US6673677B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Hofmann · Munich, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Jan 28, 2003
• Grant date: Jan 6, 2004
• Expiry date: Jan 28, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.