Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions
US6673683B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Nov 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.