Yi-Ling Chan
6Patents
4h-index
11Co-inventors
43Inventor score
Filing activity: Dec 10, 2001 → Apr 30, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6518105B1 | High performance PD SOI tunneling-biased MOSFET | Emerging Cross-Sectional Technologies | 130 | Expired |
| US6784071B2 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Emerging Cross-Sectional Technologies | 50 | Expired |
| US6673683B1 | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions | Electricity | 33 | Expired |
| US7122412B2 | Method of fabricating a necked FINFET device | Electricity | 23 | Expired |
| US6800516B2 | Electrostatic discharge device protection structure | Electricity | 1 | Expired |
| US6674130B2 | High performance PD SOI tunneling-biased MOSFET | Emerging Cross-Sectional Technologies | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.