Method of forming a gate electrode contact spacer for a vertical DRAM device
US6673686B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Aug 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches (116) of a workpiece (112). A temporary spacer adjacent gate electrode contacts (132) and pad nitride layer are removed. A spacer material is deposited over exposed portions of the workpiece (112) and over the top and sides of the gate electrode contacts (132). The spacer material is removed from the horizontal surfaces of the DRAM device (100), including the exposed portions of the workpiece (112) and the top of the gate electrode contacts (132). Spacers (144) having sidewalls sloping downwardly away from the gate electrode contacts (132) are left remaining on the gate electrode contact (132) sides, preventing voids from forming during a subsequent array top oxide deposition. Spacers may also be formed adjacent top regions of isolation trenches simultaneously with the formation of spacers (144).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.