Method of fabricating a sub-lithographic sized via
US6673714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Apr 25, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.