Memory cell and production method

US6674132B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Josef Willer · Riemerling, DE

Key dates

• Filing date: Aug 9, 2001
• Grant date: Jan 6, 2004
• Expiry date: Aug 9, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Source and drain regions are disposed between gate electrodes of adjacent memory cells. Source regions are provided with polysilicon layers, in the form of a strip, as common source lines. Drain regions are connected as bit lines through polysilicon fillings to metallic interconnects applied to the top face of the semiconductor body.