Method and apparatus for SoC design validation
US6678645B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.