Back-biasing to populate strained layer quantum wells
US6680496B1 · kind B1 · utility
13Cited by
20References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/801
Abstract
Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.