Methods for transistor gate formation using gate sidewall implantation
US6682994B2 · kind B2 · utility
2Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.