Multi-stacked memory package
US6683377B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple chip package and method of making the package allow multiple same size or different size chips to be stacked over each other, thereby creating a thin profile multi-chip package. Chips are attached to one surface of a continuous flexible substrate. The substrate has a metallization layer, which is electrically connected to the chips, such as via bond wires attached to center bond pads of the chips and to bond fingers on the metallization layer. Interconnections, such as solder balls, are attached to the other surface of the substrate and only at the portion opposite to the first chip. The substrate is folded to bring the first chip toward a second chip, which are then attached, such as with an insulative adhesive spacer. If any additional chips remain on the substrate, the substrate is folded to sequentially bring each additional chip toward the surface of the substrate opposite to the preceding chip and is secured thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.