System and method of testing non-volatile memory cells
US6684173B2 · kind B2 · utility
27Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Feb 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a screen for abnormal cells using the cell transconductance. In one embodiment, a method involves reading cells against an elevated reference current while applying an elevated gate voltage, or alternatively, reading all cells against a standard reference current while applying a nominal or elevated gate voltage, and a reduced drain voltage. The abnormal cells fail this test while normal cells pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.