Method of forming a semiconductor memory device

US6686238B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Kirk D. Prall · Boise, US
• Robert Kerr · Boise, US
• Christopher Murphy · Boise, US
• D. Mark Durcan · Boise, US

Key dates

• Filing date: Jun 27, 2001
• Grant date: Feb 3, 2004
• Expiry date: Aug 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.