Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array

US6686242B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Josef Willer · Riemerling, DE
• Ronald Kakoschke · Birkenfeld, DE

Key dates

• Filing date: Jul 26, 2001
• Grant date: Feb 3, 2004
• Expiry date: Mar 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, said metallizations being insulated from the gate region layer by the insulating spacer layers.