Memory module using DRAM package to match channel impedance
US6686762B2 · kind B2 · utility
4Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Mar 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module is described. That memory module includes a memory device and a signal trace that has an unloaded portion and a loaded portion. The loaded portion has a first section and a second section. The memory device includes an input connection and an output connection. The first section of the loaded portion of the signal trace is coupled to the input connection and the second section of the loaded portion of the signal trace is coupled to the output connection. The impedance of the loaded portion is higher than it would have been if the first and second sections had been coupled to the same memory device connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.