Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor
US6687159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Feb 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.