EEPROM flash memory erasable line by line
US6687167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Aug 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.