Substrate-on-chip packaging process
US6689638B2 · kind B2 · utility
8Cited by
8References
7Claims
0Family size
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Key dates
| Filing date | Aug 26, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Oct 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A SOC (Substrate-On-Chip) packaging process is disclosed. A layer of two-stage thermosetting mixture with solvent is coating on an upside of a substrate. Thereafter, the substrate is heated for removing solvent so that the two-stage thermosetting mixture becomes a B-stage dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better operating flexibility is obtained in the SOC packaging process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.