Method for forming a semiconductor device structure in a semiconductor layer
US6689676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.