Inventor · Clifton Park, NY, US

Daniel T. Pham

28Patents
10h-index
61Co-inventors
74Inventor score

Filing activity: Feb 22, 1999 → Mar 9, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US6838322B2 Method for forming a double-gated semiconductor device Electricity 176 Expired
US8846491B1 Forming a diffusion break during a RMG process Electricity 84 Active
US9064932B1 Methods of forming gate structures by a gate-cut-last process and the resulting structures Electricity 81 Active
US6413819B1 Memory device and method for using prefabricated isolated storage elements Electricity 61 Expired
US9064801B1 Bi-layer gate cap for self-aligned contact formation Electricity 31 Active
US8728885B1 Methods of forming a three-dimensional semiconductor device with a nanowire channel structure Electricity 20 Active
US6261978A Process for forming semiconductor device with thick and thin films Emerging Cross-Sectional Technologies 17 Expired
US6509609B1 Grooved channel schottky MOSFET Electricity 14 Expired
US7943988B2 Power MOSFET with a gate structure of different material Electricity 11 Active
US8669147B2 Methods of forming high mobility fin channels on three dimensional semiconductor devices Electricity 10 Active
US8309410B2 Power MOSFET with a gate structure of different material Electricity 9 Active
US8906754B2 Methods of forming a semiconductor device with a protected gate cap layer and the resulting device Electricity 7 Active
US6753216B2 Multiple gate transistor employing monocrystalline silicon walls Electricity 6 Expired
US9219002B2 Overlay performance for a fin field effect transistor device Electricity 6 Active
US9419137B1 Stress memorization film and oxide isolation in fins Electricity 6 Active
US9184263B2 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices Electricity 5 Active
US8853019B1 Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process Performing Operations; Transporting 5 Active
US8871582B2 Methods of forming a semiconductor device with a protected gate cap layer and the resulting device Electricity 4 Active
US9263585B2 Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same Electricity 4 Active
US7645651B2 LDMOS with channel stress Electricity 4 Active
US8877588B2 Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device Electricity 4 Active
US6949455B2 Method for forming a semiconductor device structure a semiconductor layer Electricity 3 Expired
US9263537B2 Methods of forming a semiconductor device with a protected gate cap layer and the resulting device Electricity 2 Active
US8618616B2 FinFET structures and methods for fabricating the same Electricity 2 Active
US6689676B1 Method for forming a semiconductor device structure in a semiconductor layer Electricity 1 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.